Value Engrafting DFT Quiz| Test Engineering Services

Does it hurt to have resistors skewed like this on their pads as long as they’re making contact? How could this fault be detected if it’s out of the IPC Spec?

a. Functional Test would detect this fault.
b. In-Circuit Test would detect this fault.
c. AOI would detect this fault.
d. No process would detect this fault.

Is nodal access ever needed for ICT and FPT for the isolated ("unused") pin like pin 34?

a. Nodal access is needed for shorts test coverage.
b. Nodal access is needed if pin 34 in an input.
c. Nodal access is needed if pin 34 is an output.
d. All of the above

How could you detect this misaligned Pin-Through-Hole connector? Notice that the mating connector would sit crooked if not detected.

a. Functional Test would detect this fault.
b. In-Circuit Test would detect this fault.
c. AOI would detect this fault.
d. All of the above

Is there ever a condition when more than just one access point is needed for a network?

a. One nodal access point per net is all that’s ever needed.
b. Multiple conditions exist that require more than one access point per network.

Suppose the secondary transformer coil of T2 has a 7W DC resistance (across (pins 4 & 5). Suppose a 2K "bleed"resistor is needed across pins 4 & 5. Is there any way to make that resistor testable?

a. There are no tools or techniques that would allow a 2K resistance to be measured in parallel with just 7W.
b. Boundary-Scan can measure the 2K resistance with a DFT technique.
c. AOI can measure the 2K resistance with a DFT technique.
d. ICT can measure the 2K resistance with a DFT technique.

Suppose all four TAP pins of a Microprocessor are multiplexed as shown. Would Boundary-Scan work as long as access is provided to pins 42-45? Assume this device does not use /TRST.

a. Access to the four Test Access Port pins is all that’s needed for Boundary-Scan for nodal access.
b. Other access is needed in this case because of the multiplexing.
c. Access to the RESET pin is needed.
d. Access to both Crystal pins are needed.

Since this JTAG-Compatible device has TDI, TDO, TCK, TMS, and /TRST, does the device have Boundary-Scan capabilities?

a. JTAG and Boundary-Scan are synonymous terms, so yet this device has both JTAG and Boundary-Scan.
b. Just because a device uses the TAP pins and is JTAG-compatible, it does not always have the extra B-S capabilities.

Assuming the DSP is fully B-S compatible, is there a need for nodal access for the data, address, and control lines of the μP, Buffers, PROMs, or RAMs?

a. Nodal access is needed to all address, data, and control networks for ICT to detect opens, shorts, and pin faults
b. Boundary-Scan can provide a good tests for these devices, so no nodal access is needed.
c. Boundary-Scan cannot work through buffers, so nodal access is needed.

For devices that are supposed to be missing (like R66), what (if anything) should be done to the PC Board to make AOI more easily verify the device is missing?

a. AOI can quickly and easily detect that R66 is missing without any DFT changes.
b. A square should be placed between the device pads.
c. Conductive ink should be placed between the device pads.

Is a Via a good choice for an access point? If it is filled with solder masking from the top, will that affect the test access for that network?

a. A Via is a poor choice for ICT access, and it should be avoided in preference to Test Points.
b. State-of-the-art solder mask can flow through a Via, making both sides when only applying the masking material to one side.
c. Vias often get moved upon a board re-design, so it’s a poor choice for an access point.
d. All of the above.

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Conclusion:

The 4-hour Webinar that Vaughan Carlson offers entails two sections:

A one-hour Test Tutorial to acquaint you with the state-of-the-art test techniques for all PC Board-based test equipment. You’ll learn the techniques, the lingo, and the important innovations in the Test Engineering industry.

A three-hour Design-For-Test Seminar that shows step-by-step a Checklist of DFT Guidelines coupled with a PowerPoint set of slides for each Guideline.

Contact Vaughan at his email or cell phone to discuss details!

Vaughan Carlson

VALUE Engrafting

256-426-8808 (Cell)

vaughanc@valueeng.com

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