DFT Quiz

    Quiz Question 1 Image
  1. Does it hurt to have resistors skewed like this on their pads as long as they’re making contact? How could this fault be detected if it’s out of the IPC Spec?

  2. Quiz Question 2 Image
  3. Is nodal access ever needed for ICT and FPT for the isolated ("unused") pin like pin 34?

  4. Quiz Question 3 Image
  5. How could you detect this misaligned Pin-Through-Hole connector? Notice that the mating connector would sit crooked if not detected.

  6. Quiz Question 4 Image
  7. Is there ever a condition when more than just one access point is needed for a network?

  8. Quiz Question 5 Image
  9. Suppose the secondary transformer coil of T2 has a 7W DC resistance (across (pins 4 & 5). Suppose a 2K "bleed"resistor is needed across pins 4 & 5. Is there any way to make that resistor testable?

  10. Quiz Question 6 Image
  11. Suppose all four TAP pins of a Microprocessor are multiplexed as shown. Would Boundary-Scan work as long as access is provided to pins 42-45? Assume this device does not use /TRST.

  12. Quiz Question 7 Image
  13. Since this JTAG-Compatible device has TDI, TDO, TCK, TMS, and /TRST, does the device have Boundary-Scan capabilities?

  14. Quiz Question 8 Image
  15. Assuming the DSP is fully B-S compatible, is there a need for nodal access for the data, address, and control lines of the μP, Buffers, PROMs, or RAMs?

  16. Quiz Question 9 Image
  17. For devices that are supposed to be missing (like R66), what (if anything) should be done to the PC Board to make AOI more easily verify the device is missing?

  18. Quiz Question 10 Image
  19. Is a Via a good choice for an access point? If it is filled with solder masking from the top, will that affect the test access for that network?

  20. Conclusion:

    The 4-hour Webinar that Vaughan Carlson offers entails two sections:

    • A one-hour Test Tutorial to acquaint you with the state-of-the-art test techniques for all PC Board-based test equipment. You’ll learn the techniques, the lingo, and the important innovations in the Test Engineering industry.

    • A three-hour Design-For-Test Seminar that shows step-by-step a Checklist of DFT Guidelines coupled with a PowerPoint set of slides for each Guideline.

    Contact Vaughan at his email or cell phone to discuss details!

    Vaughan Carlson

    VALUE Engrafting

    256-426-8808 (Cell)