Mastering Design-For Test is a very thorough 4-hour Design-For-Test course offered about every three weeks, check the calendar for the next class offering.
This course will teach engineers, managers, and technicians how to maximize test coverage using state-of-the-art Test Equipment. Indeed, Mastering Design-For-Test will cover all major aspects of Test Engineering to achieve optimal designs for the test equipment, including:
- Automated Optical Inspection (AOI),
- Automatic X-Ray Inspection (AXI),
- Flying Probe Test (FPT)
- Boundary-Scan Test (B-S)
- In-Circuit Testing (ICT)
- Functional Card Testing (FCT).
In order to maximize synergy among the Design Engineer,the CAD Layout Engineer, and the Test Engineer, I encourage all interested parties to attend this training for a fixed price of $500. There is not a limit for the number of attendees from a single facility.
We have several platforms (Asset Intertech, Acculogic, etc.) to provide to perform stand-alone Functional Testing with Boundary-Scan test techniques.
Mastering Design-For-Test: Course Outline.
We can support functional test development with the whole Test Stand suite, with LabView, with LabWindows, et al.
- Summary of Manufacturing process and "10X Theory" for Test Engineering.
- In-Circuit Test and Flying Probe Test tutorial.
- Boundary-Scan Test Tutorial.
- Test fixturing tutorial.
- Guidelines Access Design Guidelines.
Analog Device Design Guidelines.
- Guidelines to ensure 100% Guidelines access, included access to isolated nodes.
- Center-to-Center spacing and Test Point size guidelines.
- Power and Ground Guidelines access including Test Points for power-up.
- Review of cases where Guidelines access is not necessary.
Digital Design Guidelines.
- Designing discrete devices (such as resistors and capacitors) in such a way that they’re always testable.
- Implementing Kelvin ("4-Wire") Measurements.
- Guidelines for Polarized Caps, Batteries, and SuperCaps.
Function Test Design Guidelines.
- Configuring control pins to attain maximum fault coverage.
- Programming devices at ICT / FPT.
- Design guidelines for crystals and oscillators.
- Designing in the ability to disable feedback loops.
Mechanical Design Guidelines.
- Test Points and Eyelets for FCT debug and fault isolation.
- Using a Bed-Of-Nails for FCT.
- Booting of external PROMs.
Panelized Board Design Guidelines.
- Standard sizes, shapes, and placements for Test Points for ICT and for FPT.
- Component height restrictions for ICT and FPT.
- Special design constraints for RF-based boards.
Boundary-Scan & J-Tag Design Guidelines.
- Placement of fiducials and tooling holes for boards and their panels.
- Guidelines for safely separating boards from their panels, especially when testing is placed before de-paneling.
Automated Optical and X-Ray Inspection (AOI & AXI) Guidelines.
- Placement of a test connector for power-up, B-S pins, and compliance pins.
- Design rules for the Test Access Port pins.
- Understanding the trade-offs between chaining B-S devices and separating the B-S chains.
- Understanding the distinction between B-S and J-TAG.
- Designing memories for maximum testability using B-S.
- Placement of a white square under optional devices for AOI to quickly pick up the intentionally missing device.
- Making the spacing between IC pins to be a dark color to easily detect adjacent solder shorts.
View calendar for next Webinar
1016 W. Poplar Avenue, Suite 106-119, Collierville,
Testimonials from Customers
Mastering Design-For-Test Course
by Vaughan Carlson
Bob B, Contract Manufacturer in Florida.
"Overall, I thought the course, its structure, and the presentation were excellent. I would certainly recommend this course to others."
Rick A, OEM, Alabama
"We were surprised at the amount of useful information and the level of expertise that Vaughan was able to provide in just a four-hour DFT Seminar."
Rick M, Contract Manufacturer for Military Apps in Texas.
"This course was all I had hoped for when I contracted Vaughan to provide an on-site Design-For-Test course for twelve of our engineers."